Integrated circuits have been pivotal to accelerating progress in electronic device performance, enabling device sizes to shrink without sacrificing performance. Integrated circuits have been widely adopted for electronic devices, as opposed to designs using discrete transistors, due to various capabilities that are enabled by the integrated circuits. For example, integrated circuits can be readily mass produced, generally exhibit excellent reliability, and enable a building-block approach to circuit design.
Integrated circuits generally include a semiconductor substrate including a device, such as a transistor, disposed therein. In fact, modern integrated circuits may contain millions of transistors disposed therein. Layers of dielectric materials are formed over the semiconductor substrates and may include additional devices embedded therein (such as DRAM devices). Additionally, electrical connections between the devices in the integrated circuit are formed in the layers of dielectric materials. In particular, numerous levels of interconnect routing in the form of electrically-conductive interconnects, such as copper lines and dots, are generally embedded within the layers of dielectric material to connect the devices within the integrated circuits. Each level of interconnect routing is separated from immediately adjacent levels by the dielectric material, referred to in the art as an interlayer dielectric (ILD). Adjacent levels of interconnect routing may be embedded in distinct layers of ILD, and with the interconnect routing configured in such a way so as to ensure that dielectric material separates the adjacent interconnect routings. In this regard, the electrically-conductive interconnects of the interconnect routing can be selectively insulated from both other electrically-conductive interconnects in the same interconnect routing and from electrically-conductive interconnects in interconnect routing of adjacent levels. Likewise, electrically-conductive interconnects in adjacent levels of interconnect routing can also be selectively connected to fabricate desired circuitry in the integrated circuits.
Mass production of integrated circuits, as well as the ability to form millions of devices therein, is made possible in part due to the manner in which adjacent levels of interconnect routing and other structures are connected to each other and to the devices in the semiconductor substrate. To selectively connect adjacent levels of interconnect routing, and also to form other structures in the integrated circuits, successive patterning techniques are generally employed by which a layer of dielectric material is first formed on an underlying substrate, which may be a layer of dielectric material including an adjacent level of interconnect routing or may be the semiconductor substrate including electrical contacts for the devices therein. An etch mask is then formed and patterned over the layer of dielectric material, with the etch mask having patterned recesses that selectively expose a surface of the layer of dielectric material. Vias are then etched into the layer of dielectric material through the patterned recesses in the etch mask, with multiple cycles of masking and etching conducted depending upon the number and type of underlying dielectric layers to be etched through and further depending upon a desired configuration of vias and trenches in the layer of dielectric material. As a result of etching, a surface of the interconnect routing or electrical contact in the underlying substrate can be exposed in the vias. Etch masks are then removed and material is deposited in the vias and trenches, such as electrically-conductive material or other types of depositable material, to form embedded features within the layer of dielectric material. When the deposited material is electrically-conductive, the embedded features formed in the vias and trenches may represent a new level of interconnect routing, and may further serve to interconnect the adjacent levels of interconnect routing or electrical contacts in the underlying substrate. The patterning technique may be repeated in subsequently-formed layers of dielectric materials.
Despite the ability to mass produce integrated circuits, minor defects within integrated circuits can result in device inoperability. For example, although modern patterning techniques are robust, a single missed via or trench, and attendant failure to properly form embedded features in the missing via or trench, may cause failure of the integrated circuit. This is the case even though tens of millions of etched vias and trenches may be formed in a single integrated circuit. Thus, despite the robustness of modern patterning techniques, missed vias remain concerns.
Accordingly, it is desirable to provide processes for forming integrated circuits that address common causes of missed vias during formation of integrated circuits. In addition, it is desirable to provide such processes that can remediate missed vias even after occurrence thereof, thereby salvaging integrated circuits that may otherwise be inoperable. In addition, it is desirable to provide such processes without requiring individual identification of missed vias, which may only occur on the order of once in a million vias or less. In addition, it is desirable to provide such processes while minimizing any impact on properly-formed vias. In addition, it is desirable to provide integrated circuits formed by such processes. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.